Equivalence Checking between Pre-synthesis and Post-synthesis Programs by Using VIS

PLC (Programmable Logic Controller) [1] has been widely used to implement real-time Software in PRSs (Reactor Protection Systems). Recently, there have been attempts to implement software in RPSs by using FPGA (Field-Programmable Gate Array) [2]. In PLC-based Software development, the design programs are translated into implementation programs, and behavioral equivalence between the design and implementation is demonstrated by formal method based technique. In FPGA-based software development, the design programs are also synthesized into implementation programs. However, in this process, testing and simulation based comparison techniques are mainly used. This paper proposes a formal method based technique to demonstrate behavioral equivalence between pre-synthesis and post-synthesis programs with VIS (Verification Interacting with Synthesis) verification system [3]. We translated into BLIF-MV which is front-end of VIS, from Verilog and EDIF netlist which synthesized from the same Verilog by an automatic synthesis tool.